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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11403-2E
MEMORY
CMOS
2 x 512 K x 16 BIT SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory
MB81E161622-10/-12
CMOS 2-Bank x 524,288-Word x 16 Bit Fast Cycle Random Access Memory (FCRAM) with Single Data Rate
s DESCRIPTION
The Fujitsu MB81E161622 is a Fast Cycle Random Access Memory (FCRAM*) containing 16,777,216 memory cells accessible in a 16-bit format. The MB81E161622 features a fully synchronous operation referenced to a positive edge clock, whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81E161622 is utilized using a Fujitsu advanced FCRAM core technology and designed to improve the random access performance and the complexity of controlling regular synchronous DRAM (SDRAM) which require many wait state due to long latency constraints. The MB81E161622 is ideally suited for various embedded/consumer applications including digital AVs, printers and file storage where a large band width memory is needed. * : FCRAM is a trademark of Fujitsu Limited, Japan.
s PRODUCT LINEUP
Parameter Clock Frequency @CL = 2 Burst Mode Cycle Time Access Time From Clock RAS Cycle Time Operating Current (ICC1) Power Down Mode Current (ICC2P) Self-refresh Current (ICC6) CL = 1 CL = 2 CL = 1 CL = 2 MB81E161622 -10 100 MHz Max 15 ns Min 10 ns Min 10 ns Max 6 ns Max 30 ns Min 130 mA Max 0.6 mA Max 0.6 mA Max -12 84 MHz Max 20 ns Min 12 ns Min 14 ns Max 7 ns Max 36 ns Min 120 mA Max
MB81E161622-10/-12
s FEATURES
* * * * Single +3.3 V Supply 0.3 V tolerance LVTTL compatible I/O interface Two-bank operation Programmable burst type, burst length, and CAS latency * * * * 4 K refresh cycles every 64 ms Auto- and Self-refresh CKE power down mode Output Enable and Input Data Mask
s PACKAGE
54-pin Plastic TSOP (II) Package
Marking side
(FPT-54P-M02) (Normal Bend)
2
MB81E161622-10/-12
s PIN ASSIGNMENT
54-Pin TSOP (II) (TOP VIEW) < Normal Bend : FPT-54P-M02 >
VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE CAS RAS CS NC BA A10/AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE NC NC A9 A8 A7 A6 A5 A4 VSS
(Marking side)
s PIN DESCRIPTIONS
Symbol VCC, VCCQ VSS, VSSQ * DQ0 to DQ15 DQML, DQMU WE CAS RAS CS BA AP A0 to A10 CKE CLK NC Supply Voltage Ground Data I/O DQ MASK Write Enable Column Address Strobe Row Address Strobe Chip Select Bank Select Auto Precharge Enable Address Input Clock Enable Clock Input No Connection * Row : A0 to A10 * Column : A0 to A7 * Lower Byte : DQ0 to DQ7 * Upper Byte : DQ8 to DQ15 Function
*: These pins are connected internally in the chip. 3
MB81E161622-10/-12
s BLOCK DIAGRAM
Fig. 1 - MB81E161622 BLOCK DIAGRAM
CLK CLOCK BUFFER CKE
To each block
BANK-1 BANK-0 RAS CONTROL SIGNAL LATCH COMMAND DECODER
CS RAS CAS WE
CAS
WE
MODE REGISTER
DRAM CORE (2,048 x 256 x 16)
ROW ADDR. A0 to A9, A10/AP BA ADDRESS BUFFER/ REGISTER & BANK SELECT COLUMN ADDRESS COUNTER 11
COL. ADDR. 8 I/O
DQML, DQMU I/O DATA BUFFER/ REGISTER DQ0 to DQ15
16
VCC VCCQ VSS/VSSQ
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MB81E161622-10/-12
s FUNCTIONAL TRUTH TABLE *1
* COMMAND TRUTH TABLE *2, *3, *4 Function Device Deselect No Operation Burst Stop Read Read with Auto-precharge Write Write with Auto-precharge Bank Active Precharge Single Bank Precharge All Banks Mode Register Set *6 *6 *6 *7 *8 *8 *8, 9 *5 *5 Command DESL NOP BST READ WRIT WRITA ACTV PRE PALL MRS *6 READA CKE n-1 H H H H H H H H H H H n X X X X X X X X X X X CS H L L L L L L L L L L RAS CAS X H H H H H H L L L L X H H L L L L H H H L WE X H L H H L L H L L L BA X X X V V V V V V X X A10 (AP) X X X L H L H V L H X A9, A8 X X X X X X X V X X V A7 to A0 X X X V V V V V X X V
*1: V = Valid, L = Logic Low, H = Logic High, X = either L or H. *2: All commands assumes no CSUS command on previous rising edge of clock. *3: All commands are assumed to be valid state transitions. *4: All inputs are latched on the rising edge of the clock. *5: The NOP and DESL commands have the same effect on the part. Unless specifically noted, NOP will represent both NOP and DESL commands in later descriptions. *6: The READ, READA, WRIT and WRITA commands should be issued only after the corresponding bank has been activated (ACTV command) . Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION." *7: The ACTV command should be issued only after the corresponding bank has been precharged (PRE or PALL command) . *8: Required after power up. Refer to "POWER-UP INITIALIZATION" in section "s FUNCTIONAL DESCRIPTION." *9: The MRS command should be issued only after all banks have been precharged (PRE or PALL command) and DQ is in High-Z. Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION."
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MB81E161622-10/-12
* DQM TRUTH TABLE Function Data Write/Output Enable for Lower Byte Data Write/Output Enable for Upper Byte Data Mask/Output Disable for Lower Byte Data Mask/Output Disable for Upper Byte Command ENBL L ENBL U MASK L MASK U CKE n-1 H H H H n X X X X DQML L X H X DQMU X L X H
Note : DQML and DQMU control DQ0-7 and DQ8-15, respectively. * CKE TRUTH TABLE Current State Bank Active Function Clock Suspend Mode Entry Command *1 CSUS *1 CKE n-1 H L L *2 *2, *3 REF SELF H H L L H H L L n L L H H L H H L L H H CS RAS CAS WE BA X X X L L L H L H L H X X X L L H X H X H X X X X L L H X H X H X X X X H H H X H X H X X X X X X X X X X X X A10 (AP) X X X X X X X X X X X A9 to A0 X X X X X X X X X X X
Any Clock Suspend Continue (Except Idle) Clock Suspend Idle Idle Clock Suspend Mode Exit Auto-refresh Command Self-refresh Entry
Self Refresh Self-refresh Exit Idle Power Down Entry
*4 SELFX *3 PD
Power Down Power Down Exit
*1: The CSUS command requires that at least one bank is active. Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION." *2: The REF and SELF commands should be issued only after all banks have been precharged (PRE or PALL command) . Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION." *3: The SELF and PD commands should be issued only after the last read data have been appeared on DQ. *4: The CKE should be held High during tREFC.
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MB81E161622-10/-12
* OPERATION COMMAND TABLE (Applicable to single bank) Current CS RAS CAS WE Addr Command State H L L L L Idle L L L L L H L L L Bank Active L L L L L L H L L L Read L L L L L L H L L L L L L H H H L L L H L L H L BA, CA, AP BA, RA BA, AP AP X MODE WRIT/WRITA ACTV PRE PALL REF/SELF MRS X H H H H L L L L L X H H H H L L L L L X H H H X H H L L H H H L L X H H L L H H H L L X H H L X H L H L H L L H L X H L H L H L L H L X H L H X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA NOP NOP NOP Illegal Illegal Bank Active after tRCD NOP NOP Auto-refresh or Self-refresh Mode Register Set (Idle after tRSC) NOP NOP NOP Begin Read; Determine AP Begin Write; Determine AP Illegal Precharge Precharge Illegal Illegal NOP (Continue Burst to End Bank Active) NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, New Read; Determine AP Terminate Burst, Start Write; Determine AP Illegal Terminate Burst, Precharge Idle Terminate Burst, Precharge Idle *1 Illegal Illegal *4 *2 *1 *2 *1 *3, *5 *3, *6 *1 *2 *2
Function
(Continued)
7
MB81E161622-10/-12
Current State
CS H L L L
RAS CAS WE X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L X H L H L H L L H L X H L H L H L L H L
Addr X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE
Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS
Function NOP (Continue Burst to End Bank Active) NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, Start Read; Determine AP Terminate Burst, New Write; Determine AP Illegal Terminate Burst, Precharge Idle Terminate Burst, Precharge Idle Illegal Illegal NOP (Continue Burst to End Precharge Idle) NOP (Continue Burst to End Precharge Idle) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal *2 *2 *2 *2 *1 *2 *4
Write L L L L L L H L L Read with Autoprecharge L L L L L L L
(Continued)
8
MB81E161622-10/-12
Current State
CS H L L
RAS CAS WE X H H H H L L L L L X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L X H H L L H H H L L X H L H L H L L H L X H L H L H L L H L X H L H L H L L H L
Addr X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE
Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS
Function NOP (Continue Burst to End Precharge Idle) NOP (Continue Burst to End Precharge Idle) Illegal Illegal Illegal Illegal Illegal Illegal Illegal Illegal NOP (Idle after tRP) NOP (Idle after tRP) NOP (Idle after tRP) Illegal Illegal Illegal NOP NOP Illegal Illegal NOP (Bank Active after tRCD) NOP (Bank Active after tRCD) NOP (Bank Active after tRCD) Illegal Illegal Illegal Illegal Illegal Illegal Illegal *1 *2 *2 *2 *2 *1 *2 *2 *2 *2 *2 *2 *2
Write with Autoprecharge
L L L L L L L H L L L L L L L L L H L L L L L L L L L
Precharging
Bank Activating
(Continued)
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MB81E161622-10/-12
(Continued) Current State
Refreshing
CS H L L L L
RAS X H H L L X H H H L
CAS X H L H L X H H L X
WE X X X X X X H L X X
Addr X X X X X X X X X X
Command DESL NOP/BST
Function NOP (Idle after tREFC) NOP (Idle after tREFC)
READ/READA/ Illegal WRIT/WRITA ACTV/ PRE/PALL REF/SELF/ MRS DESL NOP BST Illegal Illegal NOP (Idle after tRSC) NOP (Idle after tRSC) Illegal
Mode Register Setting
H L L L L
READ/READA/ Illegal WRIT/WRITA ACTV/PRE/ PALL/REF/ SELF/MRS Illegal
ABBREVIATIONS : RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge *1: Entry may affect other bank. *2: Illegal to the bank in specified state; entry may be legal to the bank specified by BA, depending on the state of that bank. *3: Illegal if any bank is not idle. *4: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Refer to "TIMING DIAGRAM -11 & -12" in section "s TIMIMG DIAGRAMS." *5: The SELF command should be issued only after the last read data has been appeared on DQ. *6: The MRS command should be issued only when all DQ are in High-Z. Note: All entries in OPERATION COMMAND TABLE assume that the CKE was High during the proceeding clock cycle and the current clock cycle. Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence will be asserted after power shut down.
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MB81E161622-10/-12
* COMMAND TRUTH TABLE FOR CKE Current CKE CKE CS RAS CAS State (n-1) (n) H L Selfrefresh L L L L L L H Selfrefresh Recovery H H H H H H L L Power Down L L L L X H H H H H L X H H H H H L X H H L H H H X H L L L L X X H L L L L X X H L X L L L X X H H H L X X X H H H L X X X H X L H H X X H H L X X X X H H L X X X X H X X L H
WE X X H L X X X X X H L X X X X X H X X X X
Addr X X X X X X X X X X X X X X X X X X X X X Invalid
Function
Exit Self-refresh (Self-refresh Recovery Idle after tREFC) Exit Self-refresh (Self-refresh Recovery Idle after tREFC) Illegal Illegal Illegal NOP (Maintain Self-refresh) Invalid Idle after tREFC Idle after tREFC Illegal Illegal Illegal Illegal Invalid Exit Power Down Mode Idle NOP (Maintain Power Down Mode) Illegal Illegal Illegal *1
(Continued)
11
MB81E161622-10/-12
(Continued) Current State
CKE CKE (n-1) (n) H H H H H H H H H H H H L H H H H H L L L L L L L X H
CS H L L L L H L L L L L L X X
RAS X H L L L X H H H L L L X X
CAS X X H L L X H H L H L L X X
WE X X X H L X H L X X H L X X
Addr V V V X V X X X X X X X X X
Function Refer to the Operation Command Table. Refer to the Operation Command Table. Refer to the Operation Command Table. Auto-refresh Refer to the Operation Command Table. Power Down Power Down Illegal Illegal Illegal Self-refresh Illegal Invalid Refer to the Operation Command Table. *2
All Banks Idle
Bank Active Bank Activating Read/Write Read with Autoprecharge/ Write with Autoprecharge Clock Suspend Any State Other Than Listed Above
H
H
L
X
X
X
X
X
Begin Clock Suspend next cycle
L H L L L H H
X X H L X H L
X X X X X X X
X X X X X X X
X X X X X X X
X X X X X X X
X X X X X X X
Invalid Invalid Exit Clock Suspend next cycle Maintain Clock Suspend Invalid Refer to the Operation Command Table. Illegal
*1: CKE should be held High for tREFC period. *2: The SELF command should be issued only after the last data has been appeared on DQ. Note: All entries in "COMMAND TRUTH TABLE FOR CKE" are specified at CKE (n) state and CKE input from CKE (n-1) to CKE (n) state must satisfy the corresponding setup and hold time for CKE.
12
MB81E161622-10/-12
s FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION Three major differences between SDRAMs and conventional DRAMs are : a synchronized operation, a burst mode, and a mode register. The synchronized operation is the fundamental difference. An SDRAM uses a clock input for synchronization, while a DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each operation of a DRAM is determined by their timing phase differences while each operation of the SDRAM is determined by commands and all operations are referenced to a rising edge of a clock. Fig 2 shows the basic timing diagram differences between SDRAMs and DRAMs. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to configure the SDRAM operation and function into desired system conditions. MODE REGISTER TABLE shows how the SDRAM can be configured for system requirements by mode register programming. FCRAMTM The MB81E161622 utilizes FCRAM core technology. The FCRAM is an acronym for Fast Cycle Random Access Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs. CLOCK (CLK) and CLOCK ENABLE (CKE) All input and output signals of the SDRAM use register type buffers. A CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a rising edge of a CLK. All outputs are validated by the CLK. A CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged) , the Power Down mode (standby) is entered with CKE = Low and this will make extremely low standby current. CHIP SELECT (CS) A CS enables all command inputs, RAS, CAS, WE and address inputs. When the CS is High, command signals are negated but internal operations such as a burst cycle will not be suspended. If such a control isn't needed, the CS can be tied to ground level. COMMAND INPUT (RAS, CAS and WE) Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operations, such as Row address strobe by RAS. Instead, each combination of RAS, CAS, and WE inputs in conjunction with CS input at the rising edge of the CLK determines SDRAM operations. Refer to "s FUNCTIONAL TRUTH TABLE." ADDRESS INPUT (A0 to A10) Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of nineteen address input signals are required to decode such a matrix. The SDRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV) , eleven Row addresses are initially latched and the remainder of eight Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or a Write command (WRIT or WRITA) . BANK SELECT (BA) This SDRAM has two banks and each bank contains 512 K words by 16-bit. Bank selection by A11 occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT or WRITA) , and precharge commands (PRE or PALL) .
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MB81E161622-10/-12
DATA INPUTS AND OUTPUTS (DQ0 to DQ15) Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input : tRAC ; from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.) tCAC ; from the read command when tRCD is greater than tRCD (Min) at CL = 1. tAC ; from the clock edge after tRAC and tCAC. The polarity of the output data is identical to that of input data. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tOH) . DATA I/O MASK (DQML/DQMU) DQML and DQMU are an active high enable input and have an output disable and input mask functions. During burst cycle and when DQML/DQMU = High is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on the burst type. BURST MODE OPERATION The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and by automatically strobing column address. Access time and cycle time of Burst mode is specified as tCAC/tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which defines burst type and the burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required : Current Stage Burst Read Burst Read Burst Write Burst Write Burst Read Burst Write BURST TYPE The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps around to the least significant address ( = 0) . The interleave mode is a scrambled decoding scheme for A0 through A2. If the first access of column address is even (0) , the next address will be odd (1) , or vice-versa. Next Stage Burst Read Burst Write Burst Write Burst Read Precharge Precharge 1st Step 2nd Step Method (Assert the following command) Read Command Mask Command (Normally 3 clock cycles) Write Command after lOWD Write Command Read Command Precharge Command Precharge Command
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MB81E161622-10/-12
Burst Length 2
Starting Column Address A2 A1 A0 XX0 XX1 X00 X01 X10 X11 000 001 010 011 100 101 110 111
Sequential Mode 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
Interleave Mode 0-1 1-0 0-1-2- 3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
4
8
FULL COLUMN BURST AND BURST STOP COMMAND (BST) The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same row. If burst mode reaches the end of column address, then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read (READ) /write (WRIT) , precharge (PRE) , or burst stop (BST) commands. The selection of Auto-precharge option is illegal during the full column burst operation. The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When a read mode is interrupted by the BST command, the output will be in High-Z. For the detailed rule, please refer to "TIMING DIAGRAM-8" in section "s TIMING DIAGRAMS." When a write mode is interrupted by the BST command, the data to be applied at the same time with the BST command will be ignored. PRECHARGE AND PRECHARGE OPTION (PRE, PALL) The SDRAM memory core is the same as a conventional DRAM's, requiring precharge and refresh operations. Precharge rewrites the bit line and reset the internal Row address line and is executed by the Precharge command (PRE) . With the Precharge command, the SDRAM will automatically be in standby state after precharge time (tRP) . The precharged bank is selected by combination of AP and BA when the Precharge command is asserted. If AP = High, all banks are precharged regardless of BA (PALL) . If AP = Low, a bank to be selected by A11 is precharged (PRE) . The auto-precharge enters precharge mode at the end of burst mode of read or write without the Precharge command assertion. This auto precharge is entered by AP = High when a read or write command is asserted. Refer to "s FUNCTIONAL TRUTH TABLE." 15
MB81E161622-10/-12
AUTO-REFRESH (REF) The Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates the Precharge command internally. All banks of the SDRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be asserted every 15.6 s or a total 4096 refresh commands within a 64 ms period. SELF-REFRESH ENTRY (SELF) The Self-refresh function provides automatic refresh by an internal timer as well as the Auto-refresh and will continue the refresh function until cancelled by SELFX. The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF) . Once the SDRAM enters the self-refresh mode, all inputs except for CKE will be "don't care" (either logic high or low level state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. The SELF command should be issued only after the last read data has been appeared on DQ. Note : When the burst refresh method is used, a total of 4096 auto-refresh commands must be asserted within 4 ms prior to the self-refresh mode entry. SELF-REFRESH EXIT (SELFX) To exit the Self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No operation command (NOP) or the Deselect command (DESL) should be asserted within one tRC period. The CKE should be held High within one tRC period after tCKSP Refer to "Timing Diagram-16" in section "s TIMING DIAGRAMS" for the . detail. It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period. Note : When the burst refresh method is used, a total of 4096 auto-refresh commands must be asserted within 4 ms after the Self-refresh exit. MODE REGISTER SET (MRS) The mode register of the SDRAM provides a variety of operations. The register consists of three operation fields; Burst Length, Burst Type, and CAS latency. Refer to "s MODE REGISTER TABLE." The mode register can be programmed by the Mode Register Set command (MRS) . Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power) . The MRS command should be issued only when DQ is in High-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of the SDRAM. Refer to "POWER-UP INITIALIZATION" below. POWER-UP INITIALIZATION The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. 2. 3. 4. 5. Apply the power and start the clock. Attempt to maintain either the NOP or DESL command at the input. Maintain stable power, stable clock, and NOP condition for a minimum of 100 s. Precharge all banks by the Precharge (PRE) or Precharge All command (PALL) . Assert minimum of 2 Auto-refresh commands (REF) . Program the mode register by the Mode Register Set command (MRS) .
In addition, it is recommended that DQM and CKE track VCC to insure that output is High-Z state. The Mode Register Set command (MRS) can be set before 2 Auto-refresh commands (REF) .
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MB81E161622-10/-12
Fig. 2 - BASIC TIMING FOR CONVENTIONAL DRAM vs. SYNCHRONOUS DYNAMIC RAM < SDRAM >
Active Read/Write Precharge
CLK CKE
H H H
tSI
tHI
CS
RAS
CAS
H : Read
WE
L : Write
Address
BA RA BA CA CAS Latency = 2 BA AP (A10)
DQ
Burst Length = 4
< Conventional DRAM >
Row Address Select Column Address Select Precharge
RAS
CAS
DQ
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MB81E161622-10/-12
Fig. 3 - TIMING COMPARISON BETWEEN SDRAM AND SDR FCRAM
0
1
2
3
4
5
6
7
8
9
10
SDRAM tRC = 5 clock CL = 2
ACT
RD
PRE Q
ACT
RD
PRE Q
ACT
tRC = 75 ns
tRAC = 36 ns
SDR FCRAM tRC = 2 clock CL = 1
ACT
RDA
ACT Q
RDA
ACT Q
RDA
ACT Q
RDA
ACT Q
RDA
ACT Q
tRC = 30 ns
tRAC = 25 ns
Example of Random Cycle Operation @ 67 MHz
0
1
2
3
4
5
6
7
8
9
10
SDRAM tRC = 6 clock CL = 2
ACT
RD
PRE Q tRC = 60 ns
ACT
RD
PRE Q
tRAC = 37 ns
SDR FCRAM tRC = 3 clock CL = 2
ACT
RD
PRE
ACT Q
RD
PRE
ACT Q
RD
PRE
ACT Q
RD
tRC = 30 ns
tRAC = 26 ns
Example of Random Cycle Operation @ 100 MHz
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MB81E161622-10/-12
Fig. 4 - STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
MRS MODE REGISTER SET IDLE
SELF SELFX SELF REFRESH
REF CKE\ (PD) ACTV CKE AUTO REFRESH
POWER DOWN
BANK ACTIVE SUSPEND
CKE\ (CSUS) CKE BST BANK ACTIVE BST
WRIT CKE\ (CSUS) WRITE SUSPEND WRITE CKE
WRIT WRITA READA READ
READ
READ CKE\ (CSUS) READ CKE READA READ SUSPEND
WRIT READA WRITA
WRITA CKE\ (CSUS) WRITE SUSPEND WRITE WITH AUTO PRECHARGE
PRE or PALL
CKE
READ WITH CKE\ (CSUS) AUTO PRECHARGE CKE PRE or PALL
READ SUSPEND
PRE or PALL
POWER ON
PRE or PALL
PRECHARGE
POWER APPLIED DEFINITION OF ALLOWS Manual Input Automatic Sequence
Note: CKE\ means CKE goes Low-level from High-level 19
MB81E161622-10/-12
s BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
Second command (same bank) First command
*3 *3
MRS
ACTV
READ READA
WRIT
WRITA
PRE
PALL
REF
SELF
BST
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
tRCD
tRCD
tRCD
*4
tRCD
*4
tRAS
*3
tRAS
*3
1
READ
*1
1
1
1
1
1
*3
1
*3 *1 *1
1
READA
CL + BL
CL + BL-1 tWR tWR 1 1
CL + BL-1
*3
CL + BL-1
*3
CL + BL-1
CL + BL-1 1
WRIT
*1
tDPL
*3
tDPL
*3 *1 *1
WRITA
BL-1 + tDAL
*1, *2
BL-1 + tDAL tRP
BL-1 + tDAL 1
BL-1 + tDAL
*3
BL-1 + tDAL
*1
BL-1 + tDAL
*1, *5
PRE
tRP
*2
1
tRP
tRP
*5
1
PALL
tRP
tRP
1
1
tRP
tRP
1
REF
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
SELFX
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
*1: Assume all banks are in idle state. *2: Assume output is in High-Z state. *3: Assume tRAS (Min) is satisfied. *4: Assume no I/O conflict. *5: Assume the last data have been appeared on DQ. Illegal Command.
20
MB81E161622-10/-12
s MULTI BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Second command (other bank) First command
*4 *4, *5 *4 *4, *5
MRS
ACTV
READ READA
WRIT
WRITA
PRE
PALL
REF
SELF
BST
MRS
tRSC
tRSC
*1 *6 *6 *6 *6
tRSC
*5, *6
tRSC
*6
tRSC
tRSC
tRSC
ACTV
tRRD
*1, *3
1 1
*5
1 1
*5
1
*8
1
*8
1
*5
tRAS
*5
1
READ
*1
1 CL + BL
*1, *3
1
*5, *8
1
*5, *8
1
*5
1
*5 *1 *1
1
READA
1
*1, *3
1 1
*5
1 1
*5
1 1
*5
1 1
*5
1
*5
CL + BL-1
*5
CL + BL-1
CL + BL-1 1
WRIT
*1
1
*1, *3
1
*5
tDPL
*5 *1 *1
WRITA
BL-1 + tDAL
*1, *2
1
*1, *3
1
*6
1
*6
1
*6
1
*6
1
*5, *6
BL-1 + tDAL
*6
BL-1 + tDAL
*1
BL-1 + tDAL
*1, *7
PRE
tRP
*2
1 tRP
1
1
1
1
1 1
1 1
tRP tRP
tRP
*7
1
PALL
tRP tREFC
tRP tREFC
1
REF
tREFC
tREFC
tREFC
tREFC
tREFC
SELFX
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
*1: Assume all banks are in idle state. *2: Assume output is in High-Z state. *3: tRRD (Min) of other bank (the second command will be asserted) is satisfied. *4: Assume other bank is in active, read or write state. *5: Assume tRAS (Min) is satisfied. *6: Assume other banks are not in READA/WRITA state. *7: Assume the last data have been appeared on DQ. *8: Assume no I/O conflict. Illegal Command.
21
MB81E161622-10/-12
s MODE REGISTER TABLE
MODE REGISTER SET BA 0 A10 0 A9 0 A8 0 A7 0 A6 A5 CL A4 A3 BT A2 A1 BL A0 ADDRESS MODE REGISTER
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved 1 2 Reserved Reserved Reserved Reserved Reserved
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Length BT = 0 1 2 4 8 Reserved Reserved Reserved Full Column BT = 1 * Reserved 2 4 8 Reserved Reserved Reserved Reserved
A3 0 1
Burst Type Sequential (Wrap around, Binary-up) Interleave (Wrap around, Binary-up)
*: BL = 1 and Full Column are not applicable to the interleave mode.
22
MB81E161622-10/-12
s ABSOLUTE MAXIMUM RATINGS
Parameter Voltage of VCC Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Storage Temperature Symbol VCC, VCCQ VIN, VOUT IOUT PD TSTG Rating Min -0.5 -0.5 -50 -55 Max to +4.6 to +4.6 to +50 1.3 to +125 Unit V V mA W C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS) Parameter Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature *1 *2 Notes Symbol VCC, VCCQ VSS, VSSQ VIH VIL Ta Value Min 3.0 0 2.0 -0.5 0 Typ 3.3 0 Max 3.6 0 VCC + 0.5 0.8 +70 Unit V V V V C
*1: Overshoot limit : VIH (Max) = 4.6 V for pulse width 5 ns acceptable, pulse width measured at 50% of pulse amplitude.
4.6 V 50% of pulse amplitude VIH VIH min VIL Pulse width < 5 ns
*2: Undershoot limit : VIL (Min) = VSS - 1.5 V for pulse width 5 ns acceptable, pulse width measured at 50% of pulse amplitude.
VIH VIL max VIL 50% of pulse amplitude -1.5 V Pulse width < 5 ns
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
23
MB81E161622-10/-12
s PIN CAPACITANCE
(Ta = 25 C, f = 1 MHz) Parameter Input Capacitance, Except for CLK Input Capacitance for CLK I/O Capacitance Symbol CIN1 CIN2 CI/O Min 2.5 2.5 4.0 Typ Max 5.0 4.0 6.5 Unit pF pF pF
24
MB81E161622-10/-12
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(At recommended operating conditions unless otherwise noted.) Parameter Output High Voltage Output Low Voltage Input Leakage Current (Any Input) Symbol Condition Value Min 2.4 -5 -5 Max 0.4 5 Unit V V A A
VOH (DC) IOH = -2 mA VOL (DC) IOL = 2 mA ILI 0 V VIN VCC; All other pins not under test = 0 V 0 V VIN VCC; Data out disabled Burst Length = 4 tRC = Min for BL = 4 tCK = Min One bank active Output pin open Addresses changed up to one time during tCK (Min) 0 V VIN VIL Max VIH Min VIN VCC CKE = VIL All banks idle, tCK = Min Power down mode 0 V VIN VIL Max VIH Min VIN VCC CKE = VIL, All banks idle CLK = VIH or VIL Power down mode 0 V VIN VIL Max VIH Min VIN VCC CKE = VIH , All banks idle tCK = 15 ns NOP command only, Input signals (except to CMD) are changed one time during 30 ns 0 V VIN VIL Max VIH Min VIN VCC CKE = VIH All banks idle CLK = VIH or VIL Input signal are stable 0 V VIN VIL Max VIH Min VIN VCC
Output Leakage Current
ILO
5
MB81E161622-10 Operating Current (Average Power Supply Current) MB81E161622-12 ICC1
130 120 mA
ICC2P Precharge Standby Current (Power Supply Current) ICC2PS
0.6
mA
0.6
mA
ICC2N Precharge Standby Current (Power Supply Current)
20
mA
ICC2NS
2
mA
(Continued)
25
MB81E161622-10/-12
Parameter
Symbol
Condition CKE = VIL Any bank active tCK = Min 0 V VIN VIL Max VIH Min VIN VCC CKE = VIL Any bank active CLK = VIH or VIL 0 V VIN VIL Max VIH Min VIN VCC CKE = VIH Any bank active tCK = 15 ns NOP command only, Input signals (except to CMD) are changed one time during 30 ns 0 V VIN VIL Max VIH Min VIN VCC CKE = VIH Any bank active CLK = VIH or VIL Input signals are stable 0 V VIN VIL Max VIH Min VIN VCC tCK = Min Burst Length = 4 Output pin open All-banks active Gapless data 0 V VIN VIL Max VIH Min VIN VCC Auto-refresh; tCK = Min tREFC = Min 0 V VIN VIL Max VIH Min VIN VCC Self-refresh; tCK = Min CKE 0.2 V 0 V VIN VIL Max VIH Min VIN VCC
Value Min Max
Unit
ICC3P
1
mA
ICC3PS
1
mA
Active Standby Current (Power Supply Current) ICC3N
20
mA
ICC3NS
2
mA
MB81E161622-10 Burst mode Current (Average Power Supply Current) MB81E161622-12 ICC4
100 90 mA
Refresh Current #1 MB81E161622-10 (Average Power Supply Current) MB81E161622-12
80 70 mA
ICC5
Refresh Current #2 (Average Power Supply Current)
ICC6
0.6
mA
Notes: * All voltages are referenced to VSS. * DC characteristics are measured after following the POWER-UP INITIALIZATION procedure. * ICC depends on output termination, load conditions, clock rate, number of address and/or command change within certain period. The specified values are obtained with the output open. 26
MB81E161622-10/-12
2. AC Characteristics
* AC characteristics are measured after following the POWER-UP INITIALIZATION procedure. * AC characteristics assume tT = 1 ns and 50 of terminated load. * 1.4 V is the reference level for measuring timing of input signals. Transition times are measured between VIH (Min) and VIL (Max) . Refer to Fig. 5. * At recommended operating conditions unless otherwise noted. * BASIC CHARACTERISTICS Parameter Clock Period Clock High Time Clock Low Time Input Setup Time Input Hold Time except for CKE RAS Access Time CAS Access Time Access Time from Clock (tCK = Min) Output in Low-Z Output in High-Z Output Hold Time Time between Refresh Transition Time CKE Setup Time for Power Down Exit Time *1 *1 *1 *1 *1 *1 *2 *1, 3 *1, 3, 4 *1 *1, 5 *1, 3 *2 CL = 1 CL = 2 CL = 1 CL = 2 CL = 1 CL = 2 Symbol tCK1 tCK2 tCH tCL tSI tHI tRAC tCAC tAC1 tAC2 tLZ tHZ1 tHZ2 tOH tREFI tREF tT tCKSP MB81E161622-10 MB81E161622-12 Min 15 10 3 3 2 1 0 3 3 0.5 3 Max 25 10 10 6 10 6 15.6 64 10 Min 20 12 4 4 2 1.5 0 3 3 0.5 3 Max 34 14 14 7 14 7 15.6 64 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms ns ns
Time between Auto-Refresh command interval
*1: If input signal transition time (tT) is longer than 1 ns; [ (tT / 2) - 0.5] ns should be added to tCAC (Max) , tAC (Max) , tHZ (Max) , and tCKSP (Min) spec values, [ (tT / 2) - 0.5] ns should be subtracted from tLZ (Min) , tHZ (Min) , and tOH (Min) spec values, and (tT - 1.0) ns should be added to tCH (Min) , tCL (Min) , tSI (Min) , and tHI (Min) spec values. *2: This value is for reference only. *3: Measured under AC test load circuit shown in Fig. 4. *4: tAC also specifies the access time at burst mode except for first access at CL = 1. *5: Specified where output buffer is no longer driven.
27
MB81E161622-10/-12
* BASE VALUES FOR CLOCK COUNT/LATENCY MB81E161622 Parameter RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time RAS to RAS Bank Active Delay Time Data-in to Precharge Lead Time Data-in to Active/ Refresh Command Period Refresh Cycle Time Mode Resister Set Cycle Time CLOCK COUNT FORMULA *2 Clock Base Value Clock Period (Round up to a whole number) CL = 1 CL = 2 *1 Symbol Min tRC tRP tRAS tRCD tWR tRRD tDPL tDAL1 tDAL2 tREFC tRSC 30 10 15 10 10 10 10 15 20 50 10 -10 Max 110000 Min 36 12 20 12 12 12 12 20 24 60 12 -12 Max 110000 ns ns ns ns ns ns ns ns ns ns ns Unit
*1: tRC (Min) is not sum of tRAS (Min) and tRP (Min) . Actual clock count of tRC (lRC) must satisfy tRC (Min) , tRAS (Min) and tRP (Min) . *2: All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula : clock count equals base value divided by clock period (round up to a whole number) .
28
MB81E161622-10/-12
* LATENCY - FIXED VALUES (The latency values on these parameters are fixed regardless of clock period.) MB81E161622 MB81E161622 Unit Parameter Notes Symbol -10 -12 CKE to Clock Disable DQM to Output in High-Z DQM to Input Data Delay Last Output to Write Command Delay Write Command to Input Data Delay Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay CAS to CAS Delay (Min) CAS Bank Delay (Min) CL = 1 CL = 2 CL = 1 CL = 2 lCKE lDQZ lDQD lOWD lDWD lROH1 lROH2 lBSH1 lBSH2 lCCD lCBD 1 2 0 2 0 1 2 1 2 1 1 1 2 0 2 0 1 2 1 2 1 1 cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
29
MB81E161622-10/-12
Fig. 5 - OUTPUT LOAD CIRCUIT
R1 = 50 Output 1.4 V
CL = 30 pF
LVTTL
30
MB81E161622-10/-12
Fig. 6 - TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME
tCK
tCH 2.4 V
tCL
CLK
0.4 V
1.4 V
tSI
tHI 2.4 V 1.4 V 0.4 V tHZ tOH
Input (Control, Addr. & Data)
tAC tLZ 2.4 V
Output
0.4 V
1.4 V
Note : Reference level of input signal is 1.4 V for LVTTL. Access time is measured at 1.4 V for LVTTL. AC characteristics are also measured in this condition.
Fig. 7 - TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT
CLK
H or L tCKSP (Min) 1 clock (Min)
CKE
Command
H or L
NOP
NOP
ACTV
31
MB81E161622-10/-12
Fig. 8 - TIMING DIAGRAM, PULSE WIDTH
CLK
tRC, tRP, tRAS, tRCD, tWR, tREFI, tREFC,
Input (Control)
tDPL, tDAL, tRSC, tRRD, tCKSP COMMAND COMMAND
Note : These parameters are a limit value of the rising edge of the clock from one command input to the next input. tCKSP is the latency value from the rising edge of the CKE. Measurement reference voltage is 1.4 V.
Fig. 9 - TIMING DIAGRAM, ACCESS TIME
CLK
tRAC
RAS
tRCD tCAC
CAS
tAC 1 clock at CL = 2 tAC tAC
DQ (Output)
Q (Valid)
Q (Valid)
Q (Valid)
32
MB81E161622-10/-12
s TIMING DIAGRAMS
TIMING DIAGRAM - 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
CLK
tSI tHI tSI tHI tSI tHI
CKE
*1 lCKE (1 clock) lCKE (1 clock)* *2
1
CLK (Internal)
*2
DQ (Read)
Q1
Q2
*2 (NO CHANGE)
Q3
*2 (NO CHANGE)
Q4
DQ (Write)
D1
NOT *3 WRITTEN
D2
NOT *3 WRITTEN
D3
D4
*1: The latency of the CKE (lCKE) is one clock. *2: During the read mode, burst counter will not be incremented/decremented at the next clock of the CSUS command. Output data remains the same data. *3: During the write mode, data at the next clock of the CSUS command is ignored.
TIMING DIAGRAM - 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
CLK
tCKSP (Min) 1 clock (Min)
CKE
Command
NOP *
1
PD (NOP) *
2
H or L tREF (Max)
3 NOP *
NOP *
3
4 ACTV *
*1: The Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2: The Precharge command can be posted in conjunction with CKE after the last read data has been appeared on DQ. *3: It is recommended to apply the NOP command in conjunction with CKE. *4: The ACTV command can be latched after tCKSP (Min) + 1 clock (Min) . 33
MB81E161622-10/-12
TIMING DIAGRAM - 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS
tRCD (Min)
lCCD (1 clock)
lCCD
lCCD
lCCD
CAS
Address
ROW ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
Note : CAS to CAS delay can be one or more clock period.
TIMING DIAGRAM - 4 : DIFFERENT BANK ADDRESS INPUT DELAY
CLK
tRRD (Min)
RAS
tRCD (Min) or more
lCBD (1 clock)
lCBD
CAS
tRCD (Min) ROW ADDRESS ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS
Address
A11 (BA)
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Note : CAS Bank delay can be one or more clock period.
34
MB81E161622-10/-12
TIMING DIAGRAM - 5 : DQMU, DQML - INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQML, DQMU (@ Read)
IDQZ (2 clocks)
DQ (@ Read)
Q1
Q2
High-Z
Q4
End of burst
DQML, DQMU (@ Write)
IDQD (same clock)
DQ (@ Write)
D1
MASKED
D3
D4
End of burst
TIMING DIAGRAM - 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK
tRAS (Min)
Command
ACTV
PRECHARGE
Note : PRECHARGE means `PRE' or `PALL'.
35
MB81E161622-10/-12
TIMING DIAGRAM - 7 : READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4)
CLK
Command
PRECHARGE IROH (2 clocks)
DQ
High-Z Q1
Command
PRECHARGE IROH (2 clocks) High-Z
DQ
Q1
Q2
Command
PRECHARGE IROH (2 clocks)
DQ
Q1
Q2
Q3
High-Z
Command
PRECHARGE No effect (end of burst)
DQ
Q1
Q2
Q3
Q4
Note : In case of CL = 1, the lROH is 1 clock. In case of CL = 2, the lROH is 2 clocks. PRECHARGE means `PRE' or `PALL'.
36
MB81E161622-10/-12
TIMING DIAGRAM - 8 : READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column)
CLK
Command (CL = 1)
BST IBSH (1 clock) High-Z Qn - 2 Qn - 1 Qn
DQ
Command (CL = 2)
BST IBSH (2 clocks)
DQ
Qn - 2
Qn - 1
Qn
Qn + 1
High-Z
TIMING DIAGRAM - 9 : WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ BL = 2)
CLK
Command
BST
COMMAND
DQ
LAST Dn
Masked by BST
37
MB81E161622-10/-12
TIMING DIAGRAM - 10 : WRITE INTERRUPTED BY PRECHARGE
CLK
Command
PRECHARGE tDPL (Min) tRP (Min)
ACTV
DQ
Dn - 1
LAST Dn
MASKED by Precharge
Note : The precharge command (PRE) should be issued only after the tDPL of final data input is satisfied. PRECHARGE means `PRE' or `PALL'.
TIMING DIAGRAM - 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 2, BL = 4)
CLK
IOWD (2 clocks)
Command
READ
WRIT
DQM (DQML, DQMU)
*1
*2 IDQZ (2 clocks)
*3 IDWD (same clock)
DQ
Q1
Masked
D1
D2
*1: The First DQM makes high-impedance state High-Z between the last output and the first input data. *2: The Second DQM makes internal output data mask to avoid bus contention. *3: The Third DQM in illustrated above also makes internal output data mask. If burst read ends (the final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention.
38
MB81E161622-10/-12
TIMING DIAGRAM - 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 1, BL = 4)
CLK
tWR (Min) WRIT READ
Command
DQM (DQML, DQMU)
tCAC (Max) tAC tAC tAC
DQ
D1
D2
D3 Masked by READ
Q1
Q2
Q3
Note : The Read command should be issued after tWR of the final data input is satisfied. The write data after the READ command is masked by the READ command.
TIMING DIAGRAM - 13 : READ WITH AUTO-PRECHARGE (EXAPLE @ CL = 2, BL = 2 Applied to same bank)
CLK
Command
ACTV
READA
NOP or DESL CL + BL - 1 *
ACTV
DQM (DQML, DQMU)
DQ
Q1
Q2
*: The Next ACTV command should be issued after CL + BL - 1 from the READA command.
39
MB81E161622-10/-12
TIMING DIAGRAM - 14 : WRITE WITH AUTO-PRECHARGE (EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
CLK
tDAL (Min) (BL - 1) + tDAL *
Command
ACTV
WRITA
NOP or DESL
ACTV
DQM (DQML, DQMU) DQ
D1
D2
*: The Next command should be issued after (BL - 1) + tDAL from the WRITA command. Note : * If the final data is masked by DQM, the precharge does not start at the clock of the final data input. * Once the auto precharge command is asserted, no new command within the same bank can be issued. * The Auto-precharge command can not be invoked at full column burst operation.
TIMING DIAGRAM - 15 : AUTO-REFRESH TIMING
CLK
Command
REF *1
NOP *3
NOP *4 tREFC (Min)
NOP
REF
NOP tREFC (Min)
Command *4
BA
H or L *2
H or L *2
BA
*1: All banks should be precharged prior to the first Auto-refresh command (REF) . *2: Bank select is ignored at the REF command. The refresh address and bank select are selected by the internal refresh counter. *3: Either the NOP or DESL command should be asserted within tRC period while Auto-refresh mode. *4: Any activation command such as the ACTV or MRS commands other than the REF command should be asserted after tREFC from the last REF command.
40
MB81E161622-10/-12
TIMING DIAGRAM - 16 : SELF-REFRESH ENTRY AND EXIT TIMING
CLK
tCKSP (Min) tSI (Min)
CKE
tREFC (Min) *4
Command
NOP *1
SELF
H or L
NOP *2
SELFX
NOP *3
Command
*1: The Precharge command (PRE or PALL) should be asserted if any bank is active prior to the Self-refresh Entry command (SELF) . *2: The Self-refresh Exit command (SELFX) is latched after tCKSP (Min) . It is recommended to apply the NOP command in conjunction with CKE. *3: Either the NOP or DESL command can be used during tRC period. *4: CKE should be held high for at least one tREFC period after tCKSP .
TIMING DIAGRAM - 17 : MODE REGISTER SET TIMING
CLK
tRSC (Min)
Command
MRS
NOP or DESL
ACTV
Address
MODE
ROW ADDRESS
Note : The Mode Register Set command (MRS) should be asserted only after all banks have been precharged and DQ is in High-Z.
41
MB81E161622-10/-12
s ORDERING INFORMATION
Part Number MB81E161622-10FH MB81E161622-12FH Package Plastic TSOP (II) , 54 pin (FPT-54P-M02) Remarks
42
MB81E161622-10/-12
s PACKAGE DIMENSION
54-pin plastic TSOP (II) (FPT-54P-M02)
54 28
* : Resin protrusion. (Each side : 0.15 (.006) MAX)
Details of "A" part
0.25(.010)
0~8 INDEX LEAD No.
1 27
0.45/0.75 (.018/.030)
* 22.220.10(.875.004)
0.32 .013
+0.08 -0.07 +.003 -.003
0.16(.006)
M
1.150.05 (.045.002) (Mounting height)
11.760.20(.463.008) 10.160.10(.400.004)
"A" 0.80(.031) 0.145 -0.03 0.10(.004) 20.80(.819)REF 0.100.05 (.004.002) (Stand off) .006 -.001
+0.05 +.002
C
2000 FUJITSU LIMITED F54003S-c-2-3
Dimensions in mm (inches)
43
MB81E161622-10/-12
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0112 (c) FUJITSU LIMITED Printed in Japan

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